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LHF08CTE
6.2.7 RESET OPERATIONS
V OH
RY/BY#(R)
V OL
V IH
RP#(P)
V IL
t PLPH
(A)Reset During Read Array Mode
V OH
RY/BY#(R)
V OL
t PLRH
V IH
RP#(P)
V IL
t PLPH
(B)Reset During Block Erase, Byte Write, or Lock-Bit Configuration
2.7V/3.3V/5V
V CC
38
V IL
t 235VPH
V IH
RP#(P)
V IL
(C)RP# rising Timing
Figure 18. AC Waveform for Reset Operation
Reset AC Specifications
V CC =2.7V
V CC =3.3V
V CC =5V
Sym.
Parameter
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Unit
RP# Pulse Low Time
t PLPH
(If RP# is tied to V CC , this
specification is not applicable)
100
100
100
ns
t PLRH
t 235VPH
RP# Low to Reset during
Block Erase, Byte Write or
Lock-Bit Configuration
V CC 2.7V to RP# High
V CC 3.0V to RP# High
V CC 4.5V to RP# High
1,2
3
100
?
100
20
100
12
μs
ns
NOTES:
1. If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset
will complete within 100ns.
2. A reset time, t PHQV , is required from the latter of RY/BY# or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after V CC has been in predefined range
and also has been in stable there.
Rev. 1.3
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